As integrated circuit dimensions continue to shrink, methods of failure analysis and debug must be continually refined, both for process and for design issues. One typical failure occurs when vias or contacts (i.e., vertical conducting connections) between metallization layers are either open or shorted laterally. Locating these defective vias/contacts and diagnosing the failure mechanism is crucial to addressing the problem, whether it be in the design or the process.
Accordingly, it is necessary to be able to precisely locate shorted and open vias/contacts on both fully processed electrical test structures for process monitoring, as well as on fully processed die during design debug and to provide yield improvement. It may also occur that location of shorts and/or opens in partially processed or deprocessed test structures is needed. In both of these situations, there may be a dense array or chain of vias/contacts within which the failed cell or cells must be located. Once located, the root cause of the failure must be identified so it can be corrected.
Use of Focused Ion Beam (FIB) for the aforementioned purpose is known, as well as use of the FIB in conjunction with Voltage Contrast techniques, as a failure analysis fault isolation tool to quickly identify and localize shorted and open vias/contacts, as described below. This is described by Rosenkranz et al in Active Voltage Contrast for Failure Localization in Test Structures, Proc. ISTFA 32, November 2006, pp 316-320, which is hereby incorporated by reference.
Passive Voltage Contrast (PVC), i.e., voltage contrast where no voltage is applied to the device, is a phenomenon seen while inspecting a semiconductor device with a charged particle beam tool such as a scanning electron microscope (SEM) or a FIB, where an image is seen according to secondary electrons emitted from the sample upon exposure to the beam. Impinging charged particles tend to charge a floating metal line according to the type of impinging particles and the yield of emitted charged particles: e.g., impinging electrons will charge it negative for low energies (energies less than ˜1 keV, depending on the material) and very high energies (energies ‘>100 keV for which the penetration depth is large) where the secondary electron yield is less than 1, thereby increasing secondary electron emission. Impinging electrons with energies which produce secondary electron yields >1 will charge the floating metal line positive, thereby decreasing secondary electron emission. Impinging atoms and ions may also charge the line positive. Circuit features at a given layer have a different level of contrast depending on whether that feature has an electrical path to ground, an electrical path to another circuit element, or has an open connection. This results from differences in the charging of the feature in response to the beam, which affects the number and energy of secondary electrons emitted. A common method of fault isolation during failure analysis is to use these contrast levels to determine if a feature is incorrectly connected, which then indicates that defect such as an open or short is present. PVC locates open/short defects with much finer resolution than does light optics.
FIG. 1a illustrates the use of PVC to locate an open contact in a contact chain. Location 100, where there is a transition from bright vias/contacts 105 to dark vias/contacts 110, indicates a discontinuity in the circuit at that location, presumably due to an open or highly resistive via. FIG. 1b shows the formation of via chains relative to the surface 115 of the layer being probed. The via chain extends below the surface. If the transition from bright to dark occurs at location 100 on the surface, there is still uncertainty as to which via in region 120 is defective.
Use of FIB for PVC induces a greater contrast signal than does use of an SEM, for several reasons: 1) Both the incident positive ions from the FIB beam and the ejected secondary electrons contribute to the positive charging of the metal line, in comparison to the SEM case where there must be more secondary electrons ejected than primary electrons from the electron beam incident in order for charging to occur; 2) The number of secondary electrons ejected by a FIB tends to be higher than from an SEM at the typical energies used by each (approximately 30 keV for FIB, approximately 1 keV for SEM); and 3) The average energies of the secondary electrons from an SEM are greater than from a FIB: this means that fewer of the FIB secondary electrons will not escape the charged feature at lower levels of charging than for the SEM, because they do not have sufficient kinetic energy to escape the charged feature. For an SEM if the number of secondary electrons emitted is too low there can actually by negative charging occurring, which would increase the number of secondary electrons emitted. For an SEM, as the incident beam energy is lowered to a value of approximately 1 keV, the secondary electron emission coefficient (the ratio between the number of secondary electrons emitted to the number of incident electrons) falls below 1, with the exact value dependent on the material. Negative charging occurs when the emission coefficient falls below 1. For all of the aforementioned reasons, use of an SEM does not provide as good a voltage contrast compared with the use of FIB.
PVC imaging utilizes charging of electrically isolated conductors in comparison to the dissipation of charge in grounded conductors to provide the aforementioned contrast in the secondary electron image. A floating conductor quickly gets dark when imaging, as it becomes positively charged up and the low energy secondary electrons cannot escape. A short provides a direct conductive path to ground. This results in more secondary electrons collected and a brighter image on a grounded conductor. The secondary electron images show grounded conductors as bright and floating conductors as dark, on the background of the dielectric (which also appears dark, since with no conductivity to ground, dielectrics charge up and appear dark).
In order to obtain the VC image, the IC features to be tested must be uncovered and exposed to the charged particle beam. This is known as “deprocessing” or “delayering”. Generally, devices to be examined by SEM are deprocessed by parallel polishing to remove metal interconnects above the nodes to be examined. This mechanical lapping is generally the preferred technique, although chemical deprocessing techniques may be used also. This parallel processing is quite time consuming, since after etching each layer, the device must be returned to and viewed in an SEM to re-establish the “signal”, and then the parallel process/SEM cycle is repeated until the defect is found by VC, typically requiring several iterations.
Another weakness of the parallel process/SEM cycle is that the SEM can not identify issues in the next level, thus delayering may passes through the defect and detailed information of the defect is lost. However, most of the time, knowing the level at which the defect occurs can be sufficient to correct the fabrication process.
Use of FIB in place of SEM for VC imaging provides more flexibility in method. For example, the deprocessing can be done using parallel lapping as described above, or chemistry-assisted FIB can drive the deprocessing directly and locally. This requires selectively etching an opening using the FIB beam layer by layer until the failure is found. The FIB box, i.e., the window etched, is typically 20×20 microns. The FIB etching is generally endpointed at the top of the metal lines. The success rate of locating open vias/contacts in a chain using the FIB method outlined above is approaching 100% if the via/contact chain is truly open and not failing due to high resistance. FIB-induced passive voltage contrast is visible, i.e., provides information, only when the resistance is greater than on the order of 10E10 ohms, as described in C. R. Musil, J. L. Bartelt, and J. Meingailis, “Focused Ion Beam Microsurgery for Electronics”, IEEE Electron Device Lett EDL-7 (1986) 285.)
In order to facilitate finding defect locations, the approximate region is generally determined by scan data from testing, in order to reduce the possible number of defective nodes.
Identifying defects by PVC in test structures which are designed for that purpose can be relatively straightforward under the conditions outlined above, but identifying defects in actual circuits, for example for via chains which extend in z as described above, may be a more complex problem. To address this issue, a Simulated Passive Voltage Contrast Reference may be generated to yield an expected VC image which can be displayed next to the actual VC image. By comparing the reference image representation to what is seen in the actual VC image, defective connections can be more readily identified. The reference display is produced by processing the polygon file of the circuit design such as a GDSII file—(GDSII, invented 27 years ago, is the interchange format between chip design and mask data preparation that has been used on the majority of integrated circuits built since the format's introduction) through an algorithm that simulates the connections at a given layer to the layers below, and outputs a new polygon file with sub-layer markers indicating ground, gate, or open connections. These new layers can then be displayed by gray scale in a way that matches what should be seen in the VC image, e,g, black for open, gray for gate, white for ground. The key concept is to “slice up” conductors based on lower topology net connections. In a polygon viewer, therefore, every metallization level will have line segments assigned grayscale values to closely match the VC imaging as per the connection to the lower connections or lack thereof. When upper levels are removed there can be impact on the VC of lower levels whenever a connection net is interrupted. For example if the connection to ground for an M3 line segment was through an M4 line segment and M4 is removed then the M3 line segment would need to be represented as dark instead of bright. Refinements to the algorithm can be made to generate simulated representations of other types of circuit features to more closely match real, imaged PVC results for the fabrications process. This process is described in Fault Identification by Use of a Simulated Passive Voltage Contrast Reference CAD Display, R. Fredrickson, Proc. ASM-ISTFA 2006, which is hereby incorporated by reference.
Once the PVC inspection identifies a possible defect, mechanical nano-probing can be performed to verify the suspected short/open through the creation of I-V curves. It may be necessary to use mechanical nano-probing to inject a voltage if for some reason the VC resolution is poor, possibly due to both ends of the node floating. With the injection of voltage, passive voltage contrast becomes Active Voltage Contrast (AVC), defined as voltage contrast with an additional DC voltage injected into the device.
After the defect type and location is identified, its root cause needs to be determined so that a process or design correction can be made. The VC alone can only localize the defect to a particular via. But the defect can be of many types: e.g., if the via hole was not completely etched, that is one issue; if the via hole has a void in the fill that is another issue; if the via hole was refilled during a photomask removal process, that is still another issue; if the via hole was never etched, that is another issue. Determination of the root cause generally requires a cross sectional micrograph of the defect site, which can be performed using several methods including successive polishing by FIB (the preferred method, mentioned above), and then imaging by either SEM or FIB. When using these FIB techniques described herein for doing the VC imaging, the cross-sectioning is generally performed in situ by the FIB, and then imaged in a Field Emission SEM (FE-SEM). The clarity of the visual depiction of the defect site generally provides sufficient information to move forward with a correction in design or process. FIG. 2 illustrates an SEM of a cross-sectioned open plug, showing the failure mechanism to be a residue, most likely photoresist.
It is important to note that the cross sectioning process, either by FIB or by other means, is essentially destructive to the die, due to cutting and electrically isolating neighboring traces, as well as electrically shorting others during the trenching and polishing steps.
The use of PVC and AVC as described above is quite effective for locating open or shorted via/contact defects, since the voltage contrast is dramatic between powered and grounded features. However, it is considerably less effective for locating resistive failures such as a high-resistance “open” via/contact. Causes for this type of failure can be: process-related; design-related; due to electromigration; or due to an Electrostatic Discharge (ESD) event. A problem arising from the currently used failure analysis methods is that root cause diagnosis using cross-sectioning methods inherently destroys the structure or die. This is a highly costly and time-consuming procedure. Furthermore, if there are two defects in series, these techniques could generally not reveal them.
It would be therefore a significant advance in failure analysis if a technique for via/contact defect location and characterization could be developed which can locate resistive defects, and characterize them without destroying the structure or circuit.